/*
 * Copyright (c) 2017 Qualcomm Atheros, Inc.
 * All Rights Reserved.
 * Qualcomm Atheros Confidential and Proprietary.
 */
#define DIAG_CONFIG_PHYDBG_ADCCAPTURE					12
#define DIAG_DUMP_PHYDBG_ADCCAPTURE						13


#define BB_PHYDBG_CONTROL1_REG_ADDR 					0x1049c
#define BB_PHYDBG_CONTROL1_PHYDBG_CAP_PRE_STORE_LSB 	0
#define BB_PHYDBG_CONTROL1_PHYDBG_CAP_PRE_STORE_MSB 	13
#define BB_PHYDBG_CONTROL1_PHYDBG_CAP_PRE_STORE_MASK 	0x3000
#define BB_PHYDBG_CONTROL1_PHYDBG_PLYBCK_TRIG_MODE_LSB  14  
#define BB_PHYDBG_CONTROL1_PHYDBG_PLYBCK_TRIG_MODE_MSB  14
#define BB_PHYDBG_CONTROL1_PHYDBG_PLYBCK_TRIG_MODE_MASK 0x4000
#define BB_PHYDBG_CONTROL1_PHYDBG_CAP_TRIG_MODE_LSB		15	
#define BB_PHYDBG_CONTROL1_PHYDBG_CAP_TRIG_MODE_MSB		15	
#define BB_PHYDBG_CONTROL1_PHYDBG_CAP_TRIG_MODE_MASK	0x8000
#define BB_PHYDBG_CONTROL1_PHYDBG_PLYBCK_COUNT_LSB 		16
#define BB_PHYDBG_CONTROL1_PHYDBG_PLYBCK_COUNT_MSB 		29
#define BB_PHYDBG_CONTROL1_PHYDBG_PLYBCK_COUNT_MASK		0x3fff
#define BB_PHYDBG_CONTROL1_PHYDBG_CAP_CHN_SEL_LSB 		30	  
#define BB_PHYDBG_CONTROL1_PHYDBG_CAP_CHN_SEL_MSB 		31		
#define BB_PHYDBG_CONTROL1_PHYDBG_CAP_CHN_SEL_MASK 		0xc0000000	
  
#define BB_PHYDBG_CONTROL2_REG_ADDR 					0x104a0
#define BB_PHYDBG_CONTROL2_PHYDBG_MODE_LSB				0				
#define BB_PHYDBG_CONTROL2_PHYDBG_MODE_MSB				3
#define BB_PHYDBG_CONTROL2_PHYDBG_MODE_MASK				0xf
#define BB_PHYDBG_CONTROL2_PHYDBG_PLYBCK_EN_LSB			4
#define BB_PHYDBG_CONTROL2_PHYDBG_PLYBCK_EN_MSB			4
#define BB_PHYDBG_CONTROL2_PHYDBG_PLYBCK_EN_MASK		0x10
#define BB_PHYDBG_CONTROL2_PHYDBG_APB_AUTOINCR_LSB		5
#define BB_PHYDBG_CONTROL2_PHYDBG_APB_AUTOINCR_MSB		6
#define BB_PHYDBG_CONTROL2_PHYDBG_APB_AUTOINCR_MASK		0x60
#define BB_PHYDBG_CONTROL2_PHYDBG_FSMSTATE_LSB			7
#define BB_PHYDBG_CONTROL2_PHYDBG_FSMSTATE_MSB			10
#define BB_PHYDBG_CONTROL2_PHYDBG_FSMSTATE_MASK			0x780
#define BB_PHYDBG_CONTROL2_PHYDBG_CAP_TRIG_SELECT_LSB	11
#define BB_PHYDBG_CONTROL2_PHYDBG_CAP_TRIG_SELECT_MSB	15
#define BB_PHYDBG_CONTROL2_PHYDBG_CAP_TRIG_SELECT_MASK	0xf800
#define BB_PHYDBG_CONTROL2_PHYDBG_CAP_TRIG_ADDR_LSB		16
#define BB_PHYDBG_CONTROL2_PHYDBG_CAP_TRIG_ADDR_MSB		30
#define BB_PHYDBG_CONTROL2_PHYDBG_CAP_TRIG_ADDR_MASK	0x7ff0000
#define BB_PHYDBG_CONTROL2_PHYDBG_CAP_EN_LSB			31
#define BB_PHYDBG_CONTROL2_PHYDBG_CAP_EN_MSB			31
#define BB_PHYDBG_CONTROL2_PHYDBG_CAP_EN_MASK			0x80000000

#define BB_PHYDBG_MEM_ADDR 								0x10500
#define BB_PHYDBG_MEM_ADDR_PHYDBG_MEM_ADDR_LSB			0
#define BB_PHYDBG_MEM_ADDR_PHYDBG_MEM_ADDR_MSB			15

#define BB_PHYDBG_MEM_DATA 								0x10504
